Parametric curve generating device generating a Bezier curve for font character utilization or an arbitrary parametric curve

ABSTRACT

A parametric curve generating device for developing a Bezier curve is provided. The device is capable of executing a high speed division operation with a limited magnitude of hardware scale. Adders perform calculations that are stored in registers. Convergence discrimination circuits discriminate whether data stored in the registers converge. Subsequent processing varies depending on the discrimination result. A stack memory is used to store data from the registers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a parametric curve generating device,which generates an outline font character utilized in the officeautomation equipment such as a computer or a printer, or an arbitraryparametric curve utilized in the field of CAD, designing, etc.

2. Related Background Art

At first, as an example of the curve there will be explained a Beziercurve. A third-order Bezier curve can be represented by the followingequation, utilizing the coordinates P₀, P₁, P₂ and P₃ of four points:

    P(t)=P.sub.0 (1-t).sup.3 +3P.sub.1 t(1-t).sup.2 +3P.sub.2 t.sup.2 (1-t)+P.sub.3 t.sup.3 (0≦t≦1)

This Bezier curve (P₀ . . . P₃) can be divided into two Bezier curves(Q₀ . . . Q₃ and R₀ . . . R₃), as shown in FIG. 1, by taking insuccession the middle points of the control points (P₀ . . . P₃),wherein Q₃ =R₀. The drawing is completed by repeating such division,until the entire length of the control points becomes equal to or lessthan a bit distance 1.

The division of the initial values (P₀ . . . P₃) generates two sets ofdata, of which one set (R₀ . . . R₃) is saved in a stack and the other(Q₀ . . . Q₃) is used as the initial values of the next division. Thisoperation is repeated, and, if the data (Q₀ . . . Q₃) converge at acertain point, the data (R₀ . . . R₃) is used as the initial values forthe next operation. If both data (Q₀ . . . Q₃) and (R₀ . . . R₃)converge, the data of the control points saved immediately before in thestack are revived as the initial values for the next operation. All theoperations are completed when the stack becomes empty. Through suchprocess, there can be obtained a train of the developed drawn points ofthe Bezier curve, in a continuous manner from P₀ to P₃.

The operation of determining the middle point of two control pointsinvolves an addition and a division into 1/2. Since the 1/2 division canbe achieved by a 1-bit shift to the right, an adder can achieve theaddition and the 1/2 division by shifting the output of the adder to theright by a bit. If the data of the control points are of n bits, theresult of the 1/2 division is given by the upper (n-1) bits of theresult of addition. Also the carry-over output of the adder may be usedas the uppermost bit of the result of the calculation.

FIG. 2 shows an example of the circuit of the parametric curvegenerating device for effecting the above-mentioned 1/2 division. Theabove-mentioned data (P₀ . . . P₃) are respectively stored in registers1-4 . Adders 11-16 execute the 1/2 divisions, and the results of theoperation (Q₀ . . . Q₃, R₀ . . . R₃) are released to points 21-27 (Q₃and R₀ are same and released to a point 24).

Convergence discrimination circuits 31, 32 respectively determine |Q₀-Q₃ | and |R₀ -R₃ | and discriminate whether these values satisfy apredetermined condition of convergence, namely whether these values areequal to or less than the bit distance 1.

The function of the above-explained parametric curve generating deviceis classified into three cases according to the state of convergence ofthe control points, namely a case where (Q₀ . . . Q₃) do not converge, acase where (Q₀ . . . Q₃) converge but (R₀ . . . R₃) do not converge, anda case where (Q₀ . . . Q₃) and (R₀ . . . R₃) both converge. Suchfunction is controlled by an unrepresented control circuit.

In the case when (Q₀ . . . Q₃) do not converge, the data (Q₁. . . Q₃)released to the points 22, 23, 24 is stored in the registers 2-4 througha selector 41. The content of the register 1, being equal to Q₀, remainsunchanged. At the same time, the data (R₁. . . R₃), released to thepoints 25, 26, 27 is saved in a stack memory 61 through a bus 51, and asimilar operation is conducted on the new data (Q₁. . . Q₃).

In the case when (Q₀ . . . Q₃) converge but (R₀ . . . R₃) do notconverge, the data Q₀ released from the register 1 to the point 21 isreleased. For calculating the next points, the data (R₀ . . . R₂) at 24,25, 26 are stored in the registers 1-3 through the selector 41. Thecontent of the register 4, being equal to R₃, remains unchanged.

In the case when (Q₀ . . . Q₃) and (R₀ . . . R₃) both converge, the dataQ₀ and R₀ are released. Then, for calculating a point next to R₀, thecontent (R₃) of the register 4 is stored in the register 1 through theselector 41, and the immediately previously saved data of three pointsare stored in the registers 2-4 from the stack memory 61, through thebus 51 and the selector 41.

For operating this circuit, it is necessary to set a clock cycle in sucha manner that the 1/2 division, discrimination of convergence, switchingof the selector 41, transfer to the registers 1-4 and saving/reviving toor from the stack memory 61 can be conducted within a clock cycle. Morespecifically, disregarding the data transfer time, the above-mentionedsetting has to satisfy:

    (a clock cycle) >(delay time in an adder) ×3 +(delay time in convergence discrimination circuit) +(selector switching time) +(data set-up time of register)

and the data of three control points has to be simultaneously saved inor revived from the stack memory within this cycle time.

The data of each control point is data with a floating decimal point,consisting of an integral part of 1₀ bits and a fractional part of 1₁bits. In order to generate a Bezier curve without error, the number 1₁of bits of the fractional part has to be generally comparable with 1₀.For example, if 1₀ has 16 bits, each of the registers 1-4 and the adders11-16 of the above-explained parameter curve generating device has tohave about 32 bits, so that the magnitude of the hardware can becomelarge.

Also the stack memory 61, for simultaneously handling the data of threecontrol points, requires a port of 32×3=96 bits. Similarly, the data bus51 is required to have a width of 96 bits. The presence of a bus of suchlarge width requires a large wiring area and is disadvantageous informing this circuit into an LSI.

As explained in the foregoing, in order to execute the 1/2 divisionrequired for determining the Bezier curve at a high speed, theconventional circuit requires a large magnitude and the bus of a largewidth, and is therefore inadequate for LSI formation.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a parametric curvegenerating device for generating a Bezier curve, capable of executingthe 1/2 division at a high speed with a circuit of limited magnitude.

The above-mentioned object can be attained, according to the presentinvention, by a parametric curve generating device for generating anarbitrary parametric curve, having a first register for storing thecoordinates of the control point of the curve; a 1/2 division circuitfor dividing the control points, stored in the register, into twothereby forming control points of two curves; and a second register forstoring the control points of the two curves formed by the 1/2 divisioncircuit. The device also includes a stack memory for successivelystoring the control points of plural sets; a third register positionedbetween the first and second registers and the stack memory. The thirdregister is and adapted to store the control points of a set. The devicefurther includes a discrimination circuit for determining whether or notto effect the division of the control points by the 1/2 divisioncircuit. A desired parametric curve is generated and released byrepeating the 1/2 division on the control points given in advance to thefirst register.

The present invention is further featured by a fact that, in case one ofthe two sets of the control points formed by the 1/2 division circuit istemporarily saved according to the result of discrimination by thediscrimination circuit, the set to be saved is stored in the thirdregister and then stored in the stack memory.

The present invention is further featured by a fact that, in case thecontrol points of a temporarily saved set of the curve are transferredto the first register according to the result of discrimination by thediscrimination circuit, the content of the third register istransferred.

The present invention is further featured by a fact that the dividingoperation of the 1/2 division circuit and the transfer between the thirdregister and the stack memory are simultaneously executed in a parallelmanner.

The present invention is further featured by a fact that the stackmemory is so constructed as to read and write a control point at a time.

The present invention is further featured by a fact that the 1/2division circuit is composed of three adders and the dividing operationof each control point is completed in three clock cycles.

The present invention is further featured by a fact that each of theregisters and the stack memory is composed of an integral part and afractional part.

The present invention is further featured by a fact that the generatedcurve is a Bezier curve.

The present invention is further featured by a fact that theabove-mentioned Bezier curve belongs to a two-dimensional space having xand y coordinates, and the above-mentioned registers and stack memoryare provided for each of the x and y coordinates.

The present invention is further featured by a fact that there isprovided output means for releasing the generated curve.

The present invention is further featured by a fact that theabove-mentioned output means is a printer.

The parametric curve generating device of the present inventiongenerates a desired parameter curve, by repeating a 1/2 dividingoperation on the points of a Bezier curve given to the first registerand saving the data from the adders to the stack memory or reviving thedata from the stack memory to the adders.

The parametric curve generating device of the present invention iscapable of simultaneously executing the dividing operation of thecontrol points of the Bezier curve by the 1/2 division circuit and thesaving/reviving operation of a set of the control points to or from thestack memory in parallel manner, through the use of the third register.Owing to this configuration, each 1/2 dividing operation can beconducted within 4 clock cycles in all cases, regardless of the state ofconvergence.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing division of a third-order Beziercurve into two;

FIG. 2 is a block diagram showing the configuration of a parametriccurve generating device;

FIG. 3 is a block diagram showing the configuration of a parametriccurve generating device;

FIGS. 4 to 6 are charts showing the timing function of the various partsin FIG. 3;

FIG. 7 is a block diagram showing another configuration according to thepresent invention; and

FIGS. 8 to 10 are charts showing the timing function of the variousparts of the configuration according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows an example of the circuit embodying the present invention,wherein shown are registers 71-74 for storing the data (P₀ . . . P₃) asin the registers 1-4 explained in the foregoing; adders 81-83 which arereduced in number from six to three in comparison with the configurationshown in FIG. 2; registers 91-97 which are increased in number incomparison with the configuration in FIG. 2; a stack memory 101; and abus 111 connecting the stack memory 101 with the registers 72-74. Thiscircuit is controlled by an unrepresented control circuit.

The function of this circuit will now be explained with reference totiming charts shown in FIGS. 4, 5 and

The operations to the fourth cycle are same in FIGS. 4, 5 and 6.

In a first cycle, the adders 81-83 execute calculations Q₁ =(P₀ +P₁)/2,S =(P₁ +P₂)/2 and R₂ =(P₂ +P₃)/2, of which results Q₁, S, R₂ arerespectively stored in the registers 92, 94, 96. At the same time, P₀ istransferred as Q₀ to the register 91, and P₃ is transferred as R₃ to theregister 97.

In a second cycle, the adder 81 adds the content of the register 92 andthat of the register 94 and multiples by 1/2, and the obtained result isstored as Q₂ in the register 93. Also the adder 83 adds the contents ofthe registers 94 and 96 and multiplies by 1/2, and the obtained resultis stored as R₁ in the register 95.

In a third cycle, the adder 82 adds the contents of the register 93 and95 and multiples by 1/2, and the obtained result is stored as Q₃ (R₀) inthe register 94. At this point, Q₀ is stored in the register 91, Q₁ in92, Q₂ in 93, Q₃ =R₀ in 94, R₁ in 95, R₂ in 96, and R₃ in 97. In thismanner the 1/2 division as in FIG. 2 can be executed within three clockcycles.

In a fourth cycle, the convergence discrimination circuits 121, 122discriminate whether (Q₀ . . . Q₃) and (R₀ . . . R₃) are in theconverged state, and the process varies according to the result of thediscrimination.

FIG. 4 shows a case where (Q₀ . . . Q₃) do not converge. Based on theresult of discrimination by the convergence discrimination circuits 121,122, the selector 131 is so switched that (Q₁ . . . Q₃) are stored inthe registers 72-74 at the start of the next cycle, and (Q₁ . . . Q₃)are stored in the registers 72-74 at the start of a fifth cycle. Thecontent of the register 71, being Q₀, remains unchanged. On the otherhand, (R₁. . . R₃) are saved in succession in the stack memory 101through the bus 111, in fifth, sixth and seventh cycles. The next 1/2division cannot be started until the completion of the storage.Consequently 7 cycles are required in this case.

FIG. 5 shows a case where (Q₀ . . . Q₃) converge but (R₀ . . . R₃) donot converge. Based on the result of discrimination by the convergencediscrimination circuits 121, 122 in the fourth cycle, Q₀ is released andthe selector 131 is so switched that (R₀ . . . R₂) are stored in theregisters 71-73. (R₀ . . . R₂) are stored in the registers 71-73 at thestart of the fifth cycle. The content of the register 74, being R₃,remains unchanged. In this case 4 cycles are required, because thecontents of the registers 71-74 are fixed at the start of the fifthcycle so that the aforementioned operations of the first cycle andthereafter can be started from the fifth cycle.

FIG. 6 shows a case where (Q₀ . . . Q₃) and (R₀ . . . R₃) both converge.Based on the result of discrimination by the convergence discriminationcircuits 121, 122 in the fourth cycle, Q₀ and R₃ are released, and theselector 131 is so switched that the data of the control points can berevived in the fifth, sixth and seventh cycles and that the content ofthe register 97 can be transferred to the register 71. The data (P₁ ',P₂ ', P₃ ') of three control is revived from the stack memory 101 to theregisters 72-74 through the bus 111, in the fifth, sixth and seventhcycles. Also the content (P₀ ') of the register 97 is stored in theregister 71 through the selector 131, at the start of the fifth cycle.In this case, 7 cycles are required, as the contents of the registers71-74 are fixed at the start of the eighth cycle.

In the configuration shown in FIG. 3, the width of the data port of thestack memory 101 and of the bus 111 is 32 bits, so that it is moresuitable for LSI formation.

For operating this circuit, the clock cycle has to be set as follows,disregarding the data transfer time:

    ______________________________________    (a clock cycle) >                  max{(delay time of an adder),                  (delay time of convergence                  discrimination circuit + selector                  switching time), (stack memory                  access time)} + (register data                  set-up time)    ______________________________________

If the stack memory is composed of a register file allowing high-speedaccess, the clock cycle in FIG. 3 can be made to be about 1/4 of theclock cycle in FIG. 2. Consequently, in comparison with the circuitshown in FIG. 2, the circuit in FIG. 3 can process with a comparablespeed in case (Q₀ . . . Q₃) converge but (R₀ . . . R₃) do not converge,but is slower by the time required for the cycles for transfer with thestack memory 101 in other cases.

Another embodiment!

FIG. 7 shows another embodiment of the present invention, whereincomponents equivalent in function and position to those in FIG. 3 arerepresented by primed corresponding numbers. Registers 141-143 alone areadded to the configuration shown in FIG. 3, so that the increase in themagnitude of circuitry in this embodiment is minimal.

In the following, the function of the circuit shown in FIG. 7 will beexplained with reference to timing charts in FIGS. 8, 9 and 10. Thiscircuit is controlled by an unrepresented control circuit.

The operations to the fourth cycle are same in FIGS. 8, 9 and 10.

At first, in a first cycle, adders 81'-83' effect calculations (P₀+P₁)/2, (P₁ +P₂)/2 and (P₂ +P₃)/2, of which results Q₁, S, R₂ arerespectively stored in the registers 92', 94', 96'. At the same time, P₀is transferred as Q₀ to the register 91', and P₃ is transferred as R₃ tothe register 97'.

In a second cycle, the adder 81' adds the contents Q₁, S of theregisters 92', 94' and multiplies by 1/2, and the obtained result Q₂ isstored in the register 93'. Also the adder 83' adds the contents S, R₂of the registers 94', 96' and multiplies by 1/2, and the obtained resultR₁ is stored in the register 95'.

In a third cycle, the adder 82' adds the contents Q₂, R₁ of theregisters 93', 95' and multiplies by 1/2, and the obtained result Q₃ =R₀is stored in the register 94'. At this point, Q₀ is stored in theregister 91', Q₁ in 92', Q₂ in 93', Q₃ =R₀ in 94', R₁ in 95', R₂ in 96',and R₃ in 97'. In this manner the 1/2 division as in FIG. 2 can beexecuted within three clock cycles.

In a fourth cycle, the convergence discrimination circuits 121', 122'discriminate whether (Q₀ . . . Q₃) and (R₀ . . . R₃) are in theconverged state, and the process varies according to the result of thediscrimination.

FIG. 8 shows a case where (Q₀ . . . Q₃) do not converge. Based on theresult of discrimination by the convergence discrimination circuits121', 122', the selector 131' is so switched that (Q₁ . . . Q₃) arestored in the registers 72'-74' at the start of the fifth cycle, and (R₁. . . R₃) are stored in the registers 141-143 at the start of the fifthcycle. (Q₁ . . . Q₃) are stored in the registers 72'-74' in the fifthcycle. The content of the register 71, being Q₀, remains unchanged. Also(R₁ . . . R₃) are stored in the registers 141-143. Also in the fifth,sixth and seventh cycles, the contents of the registers 141-143 aresaved in succession in the stack memory 101', but the contents of theregisters 141-143 remain unchanged.

FIG. 9 shows a case where (Q₀ . . . Q₃) converge but (R₀ . . . R₃) donot converge. Based on the result of discrimination by the convergencediscrimination circuits 121', 122', Q₀ is released and the selector 131'is so switched that (R₀ . . . R₂) are stored in the registers 71'-73'.(R₀ . . . R₂) are stored in the registers 71'-73' at the start of thefifth cycle. The content of the register 74', being R₃, remainsunchanged.

FIG. 10 shows a case where (Q₀ . . . Q₃) and (R₀ . . . R₃) bothconverge. Based on the result of discrimination by the convergencediscrimination circuits 121', 122', Q₀ and R₀ are released, and theselector 131' is so switched that the contents (P₁ ', P₂ ', P₃ ') of theregisters 141-143 are transferred to the registers 72'-74' and thecontent (P₀ ') of the register 97' is transferred to the register 71' inthe fifth cycle. Then, at the start of the fifth cycle, the contents ofthe registers 141-143 are transferred to the registers 72'-74'. It is tobe noted that the contents of the registers 141-143 are same as thosesaved immediately before in the stack memory 101'. Also at the start ofthe fifth cycle, the content of the register 74' is stored in theregister 71' through the selector 131'. Then, in the fifth, sixth andseventh cycles, the data (P₁ ", P₂ ", P₃ ") present in the secondposition from the top of the stack memory are revived in succession tothe registers 141-143 from the stack memory 101', through the bus 111'.Also a preceding set of data is brought to the top of the stack memory.As a result, the content of the registers 141-143 always coincides withthe data of a set at the top of the stack memory 101', after each 1/2dividing operation. The content of the registers 141-143 may be used forreviving the data of the control points in the registers 72'-74' withoutwaiting for a bus cycle, even when there continues the situation where(Q₀ . . . Q₃) and (R₀ . . . R₃) both converge.

In the following there will be considered the function of this circuit,particularly with respect to:

1) bus cycle between the stack memory 101' and the registers 141-143;

2) data transfer cycle between the registers 141-143 and the registers72'-74', 95'-97'; and

3) 1/2 dividing operation.

The bus cycle occurs always in the fifth, sixth and seventh cycles.

The transfer cycle 2) always occurs at the start of the fifth cycle.

With respect to the 1/2 dividing operation 3), the data required for thenext operation is fixed in the registers 71'-74' at the start of thefifth cycle. The 1/2 dividing operation can be executed in anindependent and continuous manner, utilizing the data in the registers71'-74'.

Consequently, in the function of this circuit, a pipeline operation ispossible between the bus/transfer cycles and the 1/2 dividing operation.With such pipeline operation, each 1/2 dividing operation can beexecuted within 4 clock cycles.

In the determination of the number of necessary clock cycles, it isdefined as 4 clock cycles, utilizing the above-mentioned pipelineoperation.

Also a clock cycle can be selected comparable to that in the circuitshown in FIG. 3.

The foregoing description has been limited to the case ofone-dimensional data, but the Bezier curve relating to the presentinvention is defined in a two-dimensional space and has x and ycoordinates, and, for handling such Bezier curve, there should beprepared two sets of the parametric curve generating device explainedabove. In such case, the above-mentioned converged state is identifiedwhen x and y both converge, and the same discrimination is conducted forx and y coordinates.

The configurations shown in FIGS. 3 and 7 employ the registers 91, 97,91', 97' for the purpose of simplicity, but these registers may bedispensed with. In such case the registers 91, 91', 97, 97' are replacedby the registers 71, 71', 74, 74' respectively.

The parametric curve generating device of the present embodiment iscapable, by the entry of outline font data stored in a memory, ofderiving control points for developing a curve, developing the curvebased on thus derived control points and providing thus developed curveby an unrepresented printer or an unrepresented display device.

As explained in the foregoing, the parametric curve generating device ofthe present invention is capable of high-speed development of a Beziercurve with a limited magnitude of hardware. Also it is particularlysuitable for LSI formation, because of the reduced bus width.

What is claimed is:
 1. A curve generating apparatus connected to a busand a stack memory connected to the bus, the stack memory storingcoordinate values of control points of a curve, said apparatuscomprising:first register means for storing a coordinate value of acontrol point of a first curve; dividing means for dividing the firstcurve into a plurality of curve sections; second register means forstoring coordinate values of control points of the plurality of curvesections divided by said dividing means; third register means connectedbetween said first register means and the bus, for storing a coordinatevalue of a control point of a second curve different from the firstcurve stored in said first register means; discrimination means fordiscriminating based on the coordinate values of the control points ofthe plurality of divided curve sections stored in said second registermeans whether each of the plurality of divided curve sections is to befurther divided; and control means for controlling said first registermeans to store the coordinate value of the control point of the secondcurve stored in said third register means when said discrimination meansdiscriminates that each divided curve section is not to be furtherdivided.
 2. An apparatus according to claim 1, wherein said controlmeans controls said first register means to store the coordinate valueof the control point of one of the plurality of curve sections stored insaid second register means and controls said third register means tostore the coordinate value of the control point of another of theplurality of curve sections stored in said second register means forreturn to the stack memory when said discrimination means discriminatesthat each divided curve section is to be further divided.
 3. Anapparatus according to claim 1, wherein said control means comprises aselector circuit.
 4. A control method for a curve generating apparatusconnected to a bus and a stack memory connected to the bus, the stackmemory storing coordinate values of control points of a curve, the curvegenerating apparatus having a first register for storing a coordinatevalue of a control point of a first curve, a divider circuit fordividing the first curve into a plurality of curve sections, a secondregister for storing coordinate values of control points of theplurality of divided curve sections, and a third register connectedbetween the first register and the bus for storing a coordinate value ofa control point of a second curve different from the first curve storedin the first register, said method comprising the stepsof:discriminating based on the coordinate values of the control pointsof the plurality of divided curve sections stored in the second registerwhether each of the plurality of divided curve sections is to be furtherdivided; and controlling the first register to store the coordinatevalue of the control point of the second curve stored in the thirdregister when it is discriminated in said discriminating step that eachdivided curve section is not to be further divided.
 5. A methodaccording to claim 4, wherein said controlling step includes controllingthe first register to store the coordinate value of the control point ofone of the plurality of curve sections stored in the second register andcontrols the third register to store the coordinate value of the controlpoint of another of the plurality of curve sections stored in the secondregister for return to the stack memory it is discriminated in saiddiscriminating step that each divided curve section is to be furtherdivided.
 6. A method according to claim 4, wherein said controlling stepincludes controlling the first register with a selector circuit.